1. Field of the Invention
The present invention is related to a method for integrating CMOS devices on a semiconductor substrate.
2. Description of the Related Technology
Integrated CMOS processing involves the production of pMOSFET and nMOSFET devices (hereafter generally called ‘pMOS’ and ‘nMOS’) on a semiconductor substrate. Current research has revealed promising results for Ge pMOS devices, i.e. p-channel MOSFET transistors produced in a layer of Ge, whereas Ge nMOS devices have shown inferior performance. It is advantageous therefore to combine Si nMOS with Ge pMOS, but present research has encountered a number of technical difficulties in this area. Standard dopant activation anneals for Si are performed at temperatures typically higher than 1000° C. for high performance logic. However, the melting temperature of Ge is 937° C. Consequently, with a conventional process flow, the Si nMOS needs to be fabricated through dopant activation prior to depositing Ge. Essentially the entire front end process flow needs to be repeated for the Ge pMOS, with the associated increase in fabrication cost and the risk of adversely affecting the existing Si nMOS. Lowering the anneal temperature and annealing for longer times would be an option, but for short channel devices (channel width <˜0.5 μm) such a cooler, longer anneal would result in low dopant activation and an excessive diffusion of dopants in the tail of the junction profile. This makes it difficult to produce short channel Ge pMOS and Si nMOS in one process flow, while controlling dopant activation and diffusion.
The document “Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate”, Jia Feng et al, IEEE Elect. Dev. Lett. 27 911 (2006) describes a CMOS flow with Si nMOS and Ge pMOS. They report fabricating the Si nMOSFET using a conventional activation anneal (1050° C. RTP), then depositing the Ge and fabricating the Ge pMOSFET.
The document “Strained Si and Ge MOSFETs with High-K/Metal Gate Stack for High Mobility Dual Channel CMOS”, O. Weber et al, IEEE IEDM Tech Dig, 137 (2005) discusses CMOS, but actually describes fabrication of nMOS and pMOS on separate samples. For the CMOS emulation, a 600° C. activation anneal is done for Ge and Si. However, Weber et al. only present long channel (10 μm) device results for Si, and no indication is given as to how the method can be scaled to short channel devices. In fact, there is no indication of Ge implantation, as an amorphization process, for NMOS devices. Such an amorphization process is essential for allowing deep short channel transistor scaling with a low thermal budget. An anneal time of 15 min is specified for this work in “Etude, Fabrication et Propriétés de Transport de Transistors CMOS associant un Diélectrique Haute Permittivité et un Canal de Conduction Haute Mobilité”, O. Weber, PhD Thesis, CEA-LETI and INSA de Lyon (2005).
It is thus desirable to have an improved method for integrating Ge pMOS and Si nMOS devices in CMOS processing.